fn1320 rev 9.00 page 1 of 5 oct 4, 2005 fn1320 rev 9.00 oct 4, 2005 CA3420 0.5mhz, low supply voltage, low input current bimos operational amplifier datasheet the CA3420 is an integrated circuit operational amplifier that combines pmos transistors and bipolar transistors on a single monolithic chip. the CA3420 bimos operational amplifier features gate protec ted pmos transistors in the input circuit to provide very hi gh input impedance, very low input currents (less than 1pa). the internal bootstrapping network features a unique guardbanding technique for reducing the doubling of leaka ge current for every 10c increase in temperature. t he CA3420 operates at total supply voltages from 2v to 20v either single or dual supply. this operational amplifier is internally phase compensated to achieve stable operation in the unity gain follower configuration. additionally, i t has access te rminals for a supplementary external capacit or if additional frequency roll- off is desired. terminals are also provided for use in applications requiring input offset voltage nulling. the use of pmos in the input stage re sults in common mode input voltage capability down to 0.4 5v below the negative supply terminal, an importan t attribute for sing le supply application. the output stage uses a feedba ck ota type amplifier that can swing essentially from ra il-to-rail. the output driving current of 1.5ma (min) is prov ided by using nonlinear current mirrors. features ? 2v supply at 300 ? a supply current ? 1pa input current (typ) (e ssentially constant to 85c) ? rail-to-rail output swing (drive ? 2ma into 1k ? load) ? pin compatible with 741 operational amplifiers ? pb-free plus anneal available (rohs compliant) applications ? ph probe amplifiers ? picoammeters ? electrometer (high z) instruments ? portable equipment ? inaccessible field equipment ? battery-dependent equipmen t (medical and military) functional diagram pinout CA3420 (pdip) top view ordering information part number part marking temp. range (c) package pkg. dwg. # CA3420e CA3420e -55 to 125 8 ld pdip e8.3 CA3420ez (note) CA3420ez -55 to 125 8 ld pdip* (pb-free) e8.3 *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials a nd 100% matte tin plate termination finish, which are rohs complia nt and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak re flow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. mos bipolar x1 x1 mos bipolar ota buffer (x2) high gain (50k) buffer amps; bootstrapped input protection network - + 1 2 3 4 8 7 6 5 + v+ offset null inv. input v- non-inv. input strobe output offset null -
CA3420 fn1320 rev 9.00 page 2 of 5 oct 4, 2005 absolute maximum ratings thermal information supply voltage (v+ to v-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15v dc input voltage . . . . . . . . . . . . . . . . . . . . . . (v+ + 8v) to (v- -0.5v) input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ma output short circuit duration (note 1). . . . . . . . . . . . . . . . indefinite operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -55c to 125c thermal resistance (typical, note 2) ? ja (c/w) ? jc (c/w) pdip package* . . . . . . . . . . . . . . . . . . 105 n/a maximum junction temperatur e (plastic package) . . . . . . . 150c maximum storage temperature range . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300c *pb-free pdips can be used for through hole wave solder process ing only. they are not intended for use in reflow solder processing applications. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. short circuit may be applied to ground or to either supply. 2. ? ja is measured with the component mounted on an evaluation pc boa rd in free air. electrical specifications typical values intended only for design guidance, v supply = ? 10v, t a = 25c parameter symbol test conditions typ units input resistance r i 150 t ? input capacitance c i 4.9 pf output resistance r o 300 ? equivalent input noise voltage e n f = 1khz r s = 100 ? 62 nv/ ? hz f = 10khz 38 nv/ ? hz short-circuit current source i om +2.6ma to opposite supply sink i om -2.4ma gain bandwidth product f t 0.5 mhz slew rate sr 0.5 v/ ? s transient response rise time t r r l = 2k ? , c l = 100pf 0.7 ? s overshoot os 15 % current from terminal 8 to v- i 8 +20 ? a to v + i 8 -2ma electrical specifications for equipment design, at v supply = ? 1v, t a = 25c, unless otherwise specified parameter symbol test conditions min typ max units input offset voltage |v io | - 5 10 mv input offset current (note 3) |i io | - 0.01 4 pa input current (note 3) |i i |-15pa large signal voltage gain a ol r l = 10k ? 10 100 - kv/v 80 100 - db common mode rejection ratio cmrr - 560 1800 ? v/v 55 65 - db common mode input voltage range v lcr +0.20.5- v v lcr ---1.3- v power supply rejection ratio psrr ? v io / ? v - 100 1000 ? v/v 60 80 - db max output voltage v om +r l = ? 0.90 0.95 - v v om - -0.85 -0.91 - v supply current i+ - 350 650 ? a device dissipation p d -0.71.1 mw input offset voltage temperature drift ? v lo / ? t- 4- ? v/c note: 3. the maximum limit represents the levels obtainable on high sp eed automatic test equipment. typical values are obtained under laboratory conditions.
CA3420 fn1320 rev 9.00 page 3 of 5 oct 4, 2005 typical applications picoammeter circuit the exceptionally low input current (typically 0.2pa) makes the CA3420 highly suited for us e in a picoammeter circuit. with only a single 10g ? resistor, this circuit covers the range from ? 1.5pa. higher current ranges ar e possible with suitable switching techniques and current scaling resistors. input transient protection is provided by the 1m ? resistor in series with the input. higher current ranges require that this resisto r be reduced. the 10m ? resistor connected to pin 2 of the CA3420 decouples the potentially high input capacitance often associated with lower cur rent circuits and reduces the tendency for the circuit to oscillate under these conditions. high input resistance voltmeter advantage is taken of the hi gh input impedance of the CA3420 in a high input resistance dc v oltmeter. only two 1.5v aa type penlite batteri es power this exceedingly high-input resistance (>1,000,000m ? ) dc voltmeter. fu ll-scale deflection is ? 500mv, ? 150mv, and ? 15mv. higher voltage ranges are easily added with external input voltage attenuator networks. the meter is placed in series with the ga in network, thus eliminating the meter temperature coefficient error term. supply current in the stand by position with the meter undeflected is 300 ? a. at full-scale deflection this current rises to 800 ? a. carbon-zinc battery l ife should b e in excess of 1,000 hours. electrical specifications for equipment design, at v supply = ? 10v, t a = 25c, unless otherwise specified parameter symbol test conditions min typ max units input offset voltage |v io | - 5 10 mv input offset current (note 4) |i io | - 0.03 4 pa input current (note 4) |i i | - 0.05 5 pa large signal voltage gain a ol r l = 10k ? 10 100 - kv/v 80 100 - db common mode rejection ratio cmrr - 100 320 ? v/v 70 80 - db common mode input voltage range v lcr +8.59.3- v v lcr - -10 -10.3 - v power supply rejection ratio psrr ? v io / ? v - 32 320 ? v/v 70 90 - db max output voltage v om +r l = ? 9.7 9.9 - v v om - -9.7 -9.85 - v supply current i+ - 450 1000 ? a device dissipation p d -914 mw input offset voltage temperature drift ? v lo / ? t- 4- ? v/c note: 4. the maximum limit represents the levels obtainable on high sp eed automatic test equipment. typical values are obtained under laboratory conditions. 3 CA3420 4 500-0-500 7 +1.5v 5 1 2 -1.5v 10pf 10g ? 10m ? 1m ? battery returns 10k ? 6 m ? a ? 50pa ? 15pa ? 5pa ? 1.5pa 11k ? 1.5k ? , 1% 1.5k ? 1k ? 430 ? , 1% 150 ? , 1% 68 ? 1% - + figure 1. picoammeter circuit 2 CA3420 4 500-0-500 7 +1.5v 5 1 3 -1.5v 10m ? 22m ? battery returns 10k ? 6 m ? a ? 500mv ? 150mv ? 50mv ? 15mv 1.1k ? 1.5k ? , 1% 1.5k ? 1k ? 430 ? , 1% 150 ? , 1% 68 ? 1% - + 100pf figure 2. high input resistance voltmeter
CA3420 fn1320 rev 9.00 page 4 of 5 oct 4, 2005 typical performance curves figure 3. output voltage swing and common mode input voltage range vs supply voltage figure 4. output voltage vs load sourcing current figure 5. output voltage vs load sinking current figure 6. input n oise voltage vs frequency figure 7. open loop gain and phase shift response v o - r l = 100k ? 10 supply voltage (v) 15 t a = 25c -1.0 input & output voltage excursions from the v o + v icr - v icr + 5 1 0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 positive and negative supply voltage (v) v+ = 2v v+ = 5v v+ = 10v v+ = 20v 10 1 0.1 0.01 load (sourcing) current (ma) v- = 0v t a = 25c 1000 100 10 output stage transistor saturation voltage, q 19 (mv) v- = -2v v- = -5v v- = -10v v- = -20v 10 1 0.1 0.01 load (sinking ) current (ma) 10 100 1000 output stage transistor saturation voltage, q 17 (mv) v+ = 0v t a = 25c v s = ? 10v v s = ? 5v v s = ? 1v 10 6 frequency (hz) 10 5 10 4 10 3 10 2 10 1 1 10 100 1000 t a = 25c equivalent input noise voltage (nv/ ? hz ) frequency (hz) 10 6 10 5 10 4 10 2 10 1 1 10 3 v s = ? 5v t a = 25c r l = 10k ? c l = 0pf 0 20 40 60 80 100 -180 -135 -90 -45 0 open loop voltage gain (db) open loop phase (degrees)
fn1320 rev 9.00 page 5 of 5 oct 4, 2005 CA3420 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2000-2005. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions , the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
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